The present invention relates to spread spectrum communication employing the code division multiple access (CDMA) system, and relates in particular to a synchronization detection circuit for the acquisition of synchronization between received signals.
For radio communication, when data to be transmitted is modulated and superimposed on a carrier wave, the bandwidth occupied is spread greater than several tens of times the original bandwidth of the data to be transmitted. This broadband modulation is generally called spread spectrum communication. For spread spectrum communication, a spreading code sequence is employed in order to perform spectrum spreading modulation to spread a frequency across a broad band. When the reception side performs despreading by employing the same spreading code that the transmission side used for the spectrum spreading modulation, the reception side can extract the original data that was transmitted.
As a result of spectrum spreading modulation, data to be transmitted is changed into a signal having a low power density and an extended frequency bandwidth. By despreading this signal, the original data is recovered as a signal having a high power density, while the narrow bandwidth interference wave that was superimposed along the communication path is provided as a broadband signal having a low power density. As is described above, the advantages of spread spectrum communication are low interference, high resistance to multi-path errors, and the maintenance of communication secrecy.
In a spread spectrum-direct sequence system for spread spectrum communication, the transmission side performs spectrum spreading modulation by multiplying data by a spreading code of a higher frequency, and the reception side performs despreading, by multiplying the received signal by the same spreading code, and extracts the original data. When the spreading code used by the transmission side and the reception side differs, the despreading result is a noise signal having a low power density. Therefore, when the transmission side employs a number of different spreading codes, signals for multiple channels can be transmitted at the same time and at the same frequency. The title employed for this connection system is code division multiple access (CDMA).
FIG. 4 is a diagram showing the concept of the spread spectrum-direct sequence system for spread spectrum communication. On the transmission side, the spectrum spreading modulation is performed when a multiplier 403 is used for the multiplication of digital data 401 by a spreading code 402. On the reception side, the despreading is performed when a multiplier 413 is used for the multiplication of the received signal by a spreading code 412, which is the same as the spreading code 402. As a result, the original digital data 401 is recovered as digital data 411.
FIG. 5 is a conceptual diagram for explaining the principles of the spectrum spreading modulation in FIG. 4A and the spectrum despreading in FIG. 4B. A spreading code sequence is a sequence wherein 1 and 0 appear at random, and a wave 502 where ±1 appears at random is employed as a corresponding spreading code wave. As is shown in FIG. 5, when the spectrum spreading modulation is performed for 2-bit data 501 by using spreading code 502 having a higher frequency, a signal 503 is obtained that has the same frequency as the spreading code 502. When this signal 503 is received as a signal 513, and is multiplied by a spreading code wave 512, which is the same as the one used for the transmission, the received data 511 that is obtained is the same as the original data.
As is described above, when the transmission side has multiplied at a specific timing a specific spreading code and data to be transmitted and has generated a spreading signal, the reception side can employ the same spreading code as was used for the transmission to multiply, at the same timing, the spreading signal and thus obtain the original data. For the extraction of the original data, the reception side must know the spreading code used by the transmission side and the timing at which it was used. Therefore, for synchronization, the transmission side repetitively transmits a spreading code across a specific channel. A matched filter is used as the circuit for finding the spreading code and the timing.
FIGS. 6A and 6B are diagrams for explaining the configuration of a matched filter. FIG. 6A is a diagram showing the process employed for sampling a received signal in accordance with a sampling clock and for obtaining received data (a sampling value). FIG. 6B is a block diagram showing the configuration of a matched filter. The matched filter comprises: a tap section, wherein multiple taps (flip-flops) 611 to 614 are connected in series to constitute a shift register; multipliers 621 to 624; and adders 631 to 633. In this embodiment, a matched filter having only four taps is employed. More taps, however, may be employed. Thus, if the spreading code consisted of 256 chips, 256 taps would be provided for the structure of the matched filter. A chip represents one unit of spreading code data, and in order to distinguish a bit of data to be transmitted or received, this data unit is called a chip.
In the thus structured matched filter, received data 601 is transmitted to the tap section, while shifting the data 601 by one sample. The multipliers 621 to 624 multiply the outputs of the taps by a spreading code that is generated by a code generator, and the adders 631 to 633 add the multiplication products to obtain an output correlation value 602. When the maximum output correlation value 602 is attained, at that point the timing for the received data most nearly matches the timing for the spreading code, and at that time synchronization is acquired.
FIGS. 7A to 7D are diagrams for explaining the principle employed for the acquisition of synchronization. In FIG. 7A, the spreading code and the timing are matched relative to the received data, and the maximum correlation value is attained. In FIG. 7B, the spreading code is not matched relative to the received data, and the correlation value is reduced. In FIG. 7C, the timing is not matched relative to the received data while the spreading code is matched, and the correlation value is also reduced. In FIG. 7D, the spreading code and the timing are matched relative to the received data, but noise is superimposed on the received data, and the correlation value becomes smaller than the value in FIG. 7A.
Since some effects produced by noise along a communication path can not be avoided, generally, the correlation value is as shown in FIG. 7D. Therefore, large correlation effects can not be obtained by using the matched filter structure in FIG. 6. Therefore, as a countermeasure, an averaging process is employed. During this process, since, for the spreading spectrum modulation, data to be transmitted is multiplied by the same spreading code at a specific cycle, the correlation values of several cycles are calculated and added together (averaged), so that more reliable correlation results can be obtained.
In the actual process for digitizing a received signal, when the received signal is sampled at the chip rate for the spreading code while the timing is unknown, satisfactory process accuracy can not be expected. Thus, as a countermeasure, an oversampling method is generally employed. According to this method, the received signal is sampled at a sampling rate that is several times that of the chip rate, and for calculating the correlation value, multiple sampling results are obtained for one chip interval.
FIGS. 8A and 8B are diagrams for explaining the oversampling of a received signal. In FIG. 8A, the sampling rate is equal to the chip rate of the spreading code. In FIG. 8B, double oversampling is performed at a sampling rate that is twice that of the chip rate of the spreading code, and a sampling value that is twice that of the number of chips of spreading code is obtained as received data.
FIG. 9 is a diagram for explaining the configuration of a matched filter in the double over sampling process. The matched filter comprises: a tap section, wherein multiple taps 911 to 918 are connected in series to constitute a shift register; multipliers 921 to 928; and adders 931 to 937. In this embodiment, a matched filter of 8 taps is employed. However, if the double oversampling is to be employed for spreading code of 256 chips, 512 taps will be provided for the structure of the matched filter.
In the thus structured matched filter, data 901 obtained by the oversampling is transmitted while shifting the data 901 by one sample. The outputs of the taps 911 to 912 are the two sampling values at one chip intervals that are received last, and the outputs of the taps 913 and 914 are the two sampling values at one chip intervals that are previously received. In this manner, in the tap section, two sampling values obtained by sampling performed at two locations are arranged for each one chip interval.
The multipliers 921 to 928 multiply, for each chip, these sampling values for two phases by the spreading code generated by the code generator. The adders 931 to 937 add the multiplication products to obtain an output correlation value 902, which is the average for the received data obtained by the double oversampling. The maximum output correlation value 902 is attained when the received data and the timing of the spreading code most nearly match, and in this state, synchronization is obtained.
As is described above, by using the matched filter of the oversampling system, the correlation accuracy can be improved, compared with when the sampling is performed at the chip rate. However, since double oversampling is performed, it is apparent that the number of taps and the number of multipliers is doubled, and that, in order to constitute the matched filter, the number of adders is almost doubled.
For a matched filter of a k-times oversampling system, mk taps, mk multipliers and mk-1 adders are required when the number of chips for the spreading code is m, so that the required circuit size is about k times that required for the matched filter of a non-oversampling system.
As a first problem for the matched filter of an oversampling system, since the frequency of a sampling clock is increased and in a unit hour the amount of data to be shifted between taps is increased, there is a corresponding increase in power consumption. As a second problem, since the number of taps, the number of multipliers and the number of adders increase in proportion to the multiple of the oversampling times, the size of a LSI circuit is drastically increased.
A technique for a matched filter to resolve the first problem is disclosed in JP-A-2000-269855. According to this technique, instead of performing oversampling for data that is received by a k-times oversampling system, the k matched filters of the non-oversampling system shown in FIG. 6B are arranged in parallel, and an operating clock whose phase relative to a reference clock is delayed by a period n/k times the clock cycle is provided for the n-th matched filter.
Since with this technique a high speed operating clock is not required for the matched filter, a power consumption reduction is to be expected. However, since the circuit size does not become smaller than that provided for the matched filter of a k-times oversampling system, when compared with the matched filter of a non-oversampling system, k times the power consumption is required.
Furthermore, this technique provides no resolution for the second problem. And since on an LSI chip, such as is mounted in a CDMA handy telephone, the space occupied by a matched filter is extremely large, this is a factor that contributes greatly to unit cost. So that if a smaller LSI chip is available and is employed, in addition to a considerable power consumption reduction, an appreciable unit cost reduction can also be realized.